HDLBits-Verilog:Modules and vectors
You are given a module my_dff with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The clk port needs to be connected to all instances.
The module provided to you is: module my_dff ( input clk, input d, output q );
module top_module ( input clk, input d, output q ); wire q1,q2; my_dff md1(clk,d,q1); my_dff md2(clk,q1,q2); my_dff md3(clk,q2,q); endmodule
原文地址：https://blog.csdn.net/m0_63352623/article/details/144338768
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