HDLBits训练7

时间：2024.12.28

Fsm1

代码

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;
    always@(*)
        begin
            case(state)
                A:next_state=in?A:B;
                B:next_state=in?B:A;
            endcase
        end
 

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        if(areset) state<=B;    // State flip-flops with asynchronous reset
        else state<=next_state;
    end

    // Output logic
    // assign out = (state == ...);
assign out=state;
endmodule

运行结果

Tb/clock 

代码

module top_module ( );
    // 声明时钟信号
    reg clk;

    // 实例化dut模块
    dut dut_inst (
       .clk(clk)
    );

    // 初始化时钟信号为0
    initial begin
        clk = 0;
    end

    // 产生时钟信号，周期为10 ps
    always begin
        #5 clk = ~clk;
    end
endmodule
 

运行结果

Tb/tb1

代码

module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin
        A=0;
        B=0;
        #10 A=1;
        #5 B=1;
        #5 A=0;
        #20B=0;

    end

endmodule

运行结果

Tb/and

 

代码

module top_module();
    
    reg[1:0] in;
    wire out;
    initial
        begin
            in=2'b00;
            #10 in=2'b01;
            #10 in=2'b10;
            #10 in=2'b11;
        end
    
    andgate g1(in,out);

endmodule

运行结果

 

Tb/tb2

代码

module top_module();
    parameter clk_period=10;
    reg clk;
    initial clk=0;
    always #(clk_period/2) clk=~clk;
    wire out;
    reg in;
    reg[2:0] s;
    initial
        begin
            in=0;
            s=2;
            #10 s=6;
            #10 in=1;
            s=2;
            #10 in=0;
            s=7;
            #10 in=1;
            s=0;
            #30 in=0;
        end
    
    q7 inst_q7(clk,in,s,out);

endmodule

运行结果

Tb/tff 

代码

    module top_module ();
 
    reg clk,t,q,reset;
    
    tff tff_1(.clk(clk),.reset(reset), .t(t),.q(q));
    initial begin
          clk=0;
        forever
        #5
        clk=~clk;
    end
  initial begin
        reset = 1'b0;
        #3
        reset = 1'b1;
        #5
        reset = 1'b0;   
  end
     always@(posedge clk)begin
        if(reset)begin
            t <= 1'b0;
        end
        else begin
            t <= 1'b1;
        end
     end

endmodule

运行结果

Bugs mux2 

代码

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out  );

    assign out =sel?a:b;

endmodule

运行结果

原文地址：https://blog.csdn.net/2201_75297369/article/details/144650685

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