Count clock

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

        用计数器设计一个带am/pm的12小时时钟。该计数器通过一个CLK进行计时，用ena使能信号来驱动时钟的递增。

        reset信号将时钟复位为12：00 AM。 信号pm为0代表AM，为1代表PM。hh、mm和ss由两个BCD计数器构成hours(01~12)， minutes(00~59) , second(00~59)。Reset信号比enable信号有更高的优先级，即使没有enable信号也可以进行复位操作。

        BCD码进位时，判断条件是 if(m < 8’h59)，这里是用16进制数表示，即4位二进制数表示5，四位二进制数表示9，BCD数实际上就是十六进制数，不过是人为设置满10进1.

        BCD码（Binary-Coded Decimal‎），用4位二进制数来表示1位十进制中的0~9这10个数码，是一种二进制的数字编码形式，用二进制编码的十进制代码。

 

module top_module(
input clk,
input reset,
input ena,
output reg pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);

// 定义秒、分、时的计数器
reg [7:0] s;
reg [7:0] m;
reg [7:0] h;

// 秒计数器逻辑
always @(posedge clk) begin
    if (reset) 
        s <= 8'h00;
    else if (ena) begin
        if(s == 8'h59)
           s <=0;
        else begin
            if(s[3:0] < 4'h9)
                s[3:0] = s[3:0] + 1'h1;
        else begin
                s[3:0] = 0;
                s[7:4] = s[7:4] + 1'h1;
            end
        end
    end
end

// 分计数器逻辑
always @(posedge clk) begin
    if (reset) begin
        m <= 8'h00;
    end else if (ena && s==8'h59) begin
        if(m == 8'h59)
           m <=0;
        else begin
            if(m[3:0] < 4'h9)
                m[3:0] = m[3:0] + 1'h1;
        else begin
                m[3:0] = 0;
                m[7:4] = m[7:4] + 1'h1;
            end
        end
    end
end

// 时计数器逻辑
always@(posedge clk )
        if (reset) h <= 8'h12;
   else if(ena) begin
            if(m == 8'h59 && s == 8'h59) begin
                if(h == 8'h12)
            h <= 8'h01;
            else  
                if(h[3:0] < 4'h9) begin
                    h[3:0] <= h[3:0] + 1'h1; 
                 end
                else begin
                       h[3:0] <= 0;
                       h[7:4] <= h[7:4] + 1'h1;
                 end 
            end
                                
        end
always@(posedge clk )
             if (reset) pm <= 0;
    else if(hh ==  8'h11 && mm == 8'h59 && ss == 8'h59)
        pm =!pm;
// 输出赋值
assign hh = h;
assign mm = m;
assign ss = s;
endmodule

原文地址：https://blog.csdn.net/qq_38471068/article/details/142920600

免责声明：本站文章内容转载自网络资源，如本站内容侵犯了原著者的合法权益，可联系本站删除。更多内容请关注自学内容网（zxcms.com）！