Exams/ece241 2014 q4

Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.

Build this circuit.

错误代码：

module top_module (
    input clk,
    input x,
    output z
); 
reg q1,q2,q3;
    initial begin
        q1 =0;
        q2 =0;
        q3 =0;
    end
    always @(posedge clk)begin
    q1 <= x^q1;
        q2<= x&~q2;
        q3 <= x|~q3;
    
       z = ~(q1|q2|q3);
    
   end
endmodule

因为always 内语句是同时执行所以存在 z 输出不对的情况。

module top_module (
    input clk,
    input x,
    output z
); 
reg q1,q2,q3;
    initial begin
        q1 =0;
        q2 =0;
        q3 =0;
    end
    always @(posedge clk)begin
    q1 <= x^q1;
        q2<= x&~q2;
        q3 <= x|~q3;
     end
      assign  z = ~(q1|q2|q3);
    
  
endmodule

原文地址：https://blog.csdn.net/qq_38471068/article/details/142636888

免责声明：本站文章内容转载自网络资源，如本站内容侵犯了原著者的合法权益，可联系本站删除。更多内容请关注自学内容网（zxcms.com）！