CIrcuits--Sequential--Finite_1

1.  Simple FSM1 asy reset

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        case(state)
            A:
                begin
                    if(in==1'b1) next_state=A;
                    if(in==1'b0) next_state=B;
                end
            B:
                begin
                    if(in==1'b1) next_state=B;
                    if(in==1'b0) next_state=A;
                end
        endcase
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        if(areset)
            state<=B;
        else
            state<=next_state;
    end

    assign out=state;

endmodule

2. Simple FSM1 sy reset

module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    parameter A=0;
    parameter B=1;

    reg present_state, next_state;

    always@(*)
        begin
           case (present_state)
                A:
                    begin
                        if(in==1'b1) next_state=A;
                        if(in==1'b0) next_state=B;
                    end
                B:
                    begin
                        if(in==1'b1) next_state=B;
                        if(in==1'b0) next_state=A;
                    end
            endcase 
        end
    
    always @(posedge clk) begin
        if (reset) begin  
            present_state=B;
        end else begin
            // State flip-flops
            present_state = next_state;             
        end
    end
    
    assign out=present_state;

endmodule

原文地址：https://blog.csdn.net/pmlcreating/article/details/137623482

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