RV1106B ARM Cortex-A7+MCU+512Mb-2Gb，0.5T算力，4K25fps
Chapter 1 Introduction
1.1 Overview
RV1106B is a highly integrated vision processor SoC for IPC, especially for AI related
application.
It is based on single-core ARM Cortex-A7 32-bit core which integrates NEON and FPU.
The build-in NPU supports INT8 hybrid operation and computing power is up to 0.5TOPs. In
addition, with its strong compatibility, network models based on a series of frameworks
such as TensorFlow/MXNet/PyTorch/Caffe can be easily converted.
RV1106B introduces a new generation totally hardware-based maximum 5-Megapixel ISP
(image signal processor). It implements a lot of algorithm accelerators, such as HDR, 3A,
LSC, 3DNR, 2DNR, sharpening, dehaze, gamma correction and so on. Cooperating with two
MIPI CSI interface, users can build a system that receives video data from two camera
sensors simultaneously.
The video encoder embedded in RV1106B supports H.265/H.264 video encoding and the
multi-stream encoding is supported also. With the help of this feature, the video from
camera can be encoded with higher resolution and stored in local memory and transferred
another lower resolution video to cloud storage at the same time.
RV1106B has a build-in 16-bit DRAM DDR2/DDR3L capable of sustaining demanding
memory bandwidths. Also the RTC, POR and Audio Codec are integrated in RV1106B.
1.2 Features
1.2.1 Application Processor
Single core ARM Cortex-A7
Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced
SIMD
Separately Integrated Neon and FPU
32KB L1 I-Cache and 32KB L1 D-Cache
Unified 128KB L2 Cache for Cortex-A7
TrustZone technology support
1.2.2 Memory Organization
Internal on-chip memory
Bootrom
Support system boot from the following device:
SPI interface
eMMC interface
SD/MMC interface
Support system code download by the following interface:
USB2.0 interface
UART interface
32KB system SRAM
8KB PMU SRAM
RV1106BG1 SIP 512Mb DDR2
RV1106BG2 SIP 1Gb DDR3L
RV1106BG3 SIP 2Gb DDR3L
External off-chip memory
eMMC Interface
Fully compliant with JEDEC eMMC 4.51 specification
Support HS200, but not support CMD Queue
Support two data bus width mode: 1bit and 4bits
SD/MMC Interface
Compatible with SD3.0, MMC ver4.51
Support 1bit, 4bits data bus width
Flexible Serial Flash Interface (FSPI0)
Support transfer data from/to serial flash device
Support 1bit, 2bits or 4bits data bus width
1.2.3 System Component
HPMCU
MCU in integrate 16KB Cache
Integrated Programmable Interrupt Controller, all IRQ lines connected to GIC for
CPU also connect to MCU
Integrated Debug Controller with JTAG interface
LPMCU
Integrated Programmable Interrupt Controller, all IRQ lines connected to GIC for
CPU also connect to MCU
Integrated Debug Controller with JTAG interface
Used for low power application
CRU (clock & reset unit)
Support total 2 PLLs to generate all clocks
One oscillator with 24MHz clock input
Support clock gating control for individual components
Support global soft-reset control for whole chip, also individual soft-reset for each
component
PMU (power management unit)
Multiple configurable work modes to save power by different frequency or
automatic clock gating control or power domain on/off control
Lots of wakeup sources in different mode
Support 3 separate voltage domains
，
CPU_NPU_DVDD,VDD_LOGIC,VDD_PMU.
Timer
Support 2 secure timers with 64bits counter and interrupt-based operation
Support 6 non-secure timers with 64bits counter and interrupt-based operation
Support 1 non-secure timers with 64bits counter for low power mode application
Support two operation modes: free-running and user-defined count for each timer
Support timer work state checkable
Watchdog
32-bit watchdog counter
Counter counts down from a preset value to 0 to indicate the occurrence of a
timeout
WDT can perform two types of operations when timeout occurs:
Generate a system reset
First generate an interrupt and if this is not cleared by the service routine by
the time a second timeout occurs then generate a system reset
One Watchdog for non-secure application
One Watchdog for secure application
Interrupt Controller
Support 128 SPI interrupt sources input from different components inside RV1106B
Support 16 software-triggered interrupts
Input interrupt level is fixed, high-level sensitive or rising edge sensitive
Support different interrupt priority for each interrupt source, and they are always
software-programmable
DMAC
Support 2 physical channels
Support 12 hardware requests from peripherals
Support 16 logic channels, each logic channel support the following feature
Support the data transfer of memory-to-memory, memory-to-peripherals,
peripherals-to-memory
Support Linked list DMA function to complete scatter-gather transfer
Supports three kinds of multi-block transfer: contiguous address, auto reload,
link list
Secure System
Embedded cipher engines
Support SHA-1, SHA-256/224 with hardware padding
Support HMAC, AEC CBC MAC, AES CMAC
Support AES-128, AES-192, AES-256 encrypt & decrypt cipher
Support AES ECB/CBC/OFB/CFB/CTR/CTS/XTS/GCM/CBC-MAC/CMAC mode
Support up to 4096 bits PKA mathematical operations for RSA/ECC/SM2
Support generating random numbers
Support secure OTP
Support secure debug
Support secure OS
Except CPU, the other masters in the SoC can also support security and non
security mode by software-programmable
Some slave components in SoC can only be addressed by security master and the
other slave components can be addressed by security master or non-security
master by software-programmable
System SRAM, part of space is addressed only in security mode
External DDR space can be divided into 8 parts, each part can be software
programmable to be enabled by each master
Mailbox
One Mailbox in SoC used to service Cortex-A7 and HPMCU communication, another
is used for Cortex-A7 and LPMCU communication.
Support four mailbox elements, each element includes one data word, one
command word register and one flag bit that can represent one interrupt
Provide 32 lock registers for software to use to indicate whether mailbox is
occupied
Decompression
Support for decompressing GZIP files
Support the limit size function of the decompressed data to prevent the memory
from being maliciously destroyed during the decompression process
Real Time Clock (RTC)
Provides year, month, day, weekday, hours, minutes, and seconds based on a
32.768 kHz crystal oscillator
Support compensation for the second and hour count
BCD representation of time, calendar and alarm
12- or 24-hour clock with AM and PM in 12-hour mode
Interrupts are separately software maskable
Alarm interrupt
Periodic interrupt
Chip power off interrupt
Battery power atypical interrupt
1.2.4 AOV(Always On Video) subsystem
One SPI slave interface for receiving data from camera
Dedicated SPI master for external flash device access
Low power control unit for power saving
LPMCU is used for system control
1.2.5 Video CODEC
Video Encoder
HEVC Main Profile, Level 5.0 High Tier
H.264 High Profile, level 5.0
JPEG Baseline
Support up to 2880x1620@30fps
Bitrate up to 200Mbps with CBR/VBR/FixQP/QPMAP bitrate control
YUV444, YUV420 and YUV400 format
Slice split
Area and block mapping ROI
8-area OSD
Link table configuration mode
YUV/RGB video source with crop, rotation and mirror
Ultra-low delay encoding
Motion and Occlusion Detection
1.2.6 Neural Process Unit
Neural network acceleration engine with processing performance up to 0.5 TOPS
Support integer 8 operation
Support creating simple custom operators
Support deep learning frameworks: TensorFlow, Caffe, Tflite, Pytorch, Onnx NN,
Android NN, etc.
1.2.7 2D Graphics Engine
2D Graphics Engine
Input data:
RGB888/RGB565
YUV422-P/YUV422-SP-8bit
YUV420-P/YUV420-SP-8bit
YUV444I/YUV444SP-8bit
YVYU422-8bit
YUV400-8bit
Output data:
RGB888/RGB565
YUV420/YUV422 P/SP
YUV400
YUV444SP/444I
Pixel Format conversion, BT.601/BT.709
Max resolution: 2880x1620 source, 2880x1620 destination
Scaling
Down-scaling: Average filter/Bilinear filter
Up-scaling: Bi-cubic filter(Horizontal ), Bilinear filter(Vertical )
Arbitrary non-integer scaling ratio, from 1/16 to 16
Rotation
0, 90, 180, 270-degree rotation
x-mirror, y-mirror
Mirroring and rotation co-operation
BitBLT
Block transfer
Color fill
Transparency mode (color keying/stencil test, specified value/value range)
1.2.8 Video Input Interface
MIPI Interface
Two MIPI CSI DPHY
Each MIPI DPHY V1.2, 2lanes, 1.5Gbps per lane
Support to combine 2 DPHY together to one 4lanes
Video Capture (VICAP)
Support receiving two groups of MIPI CSI interfaces, up to four IDs for each group
Support VC/DT configurable for each ID
Support ten MIPI CSI data formats: RAW8/10/12/14/16, RGB888, YUV422 8bit,
YUV422 8bit interlaced, YUV420 8bit, Legacy YUV420 8bit
Support three modes of MIPI CSI HDR: virtual channel mode, identification code
mode, line counter mode
Support RAW rounding
Support window cropping
Support reducing frame rate
Support compact/non-compact output format for RAW data
Support NV16/NV12/YUV400/YUYV output format for YUV data
Support virtual stride when write to DDR
Support DMA wrap mode
Support DMA burst gather 2/4/8
Support QOS(hurry/press)
Support sending RAW data directly to ISP
Image Signal Process (ISP)
Maximum input: 2880x1620@30fps
Minimum input: 264x264
Auto Enhance (AE)/Histogram and Auto White Balance (AWB)
BLC: Black Level Correction
DPCC: Static/Dynamic Defect Pixel Cluster Correction
LSC: Lens Shading Correction
Bayer-2DNR: Spatial Bayer-raw Noise Reduction
Bayer-3DNR: Temporal Bayer-raw Noise Reduction
CAC: Chromatic Aberration Correction
HDR-Merge: 2-Frame Merge into High-Dynamic Range
HDR-DRC: HDR Dynamic Range Compression, Tone mapping
GIC: Green Imbalance Correction
DeBayer: Advanced Adaptive Demosaic
CCM/CSM: Color Correction Matrix, RGB2YUV, etc.
Gamma: Gamma out correction
HSV: Hue, Saturation,Value Color Palette for Customer
LDCH: Lens Distortion Correction only in the Horizontal direction
YNR: Spatial luma Noise Reduction in YUV domain
CNR: Spatial chroma Noise Reduction in YUV domain
Dehaze/Enhance: Automatic Dehaze and effect enhancement
localHist
：
local Histogram to Enhance local contrast
Sharp: Image sharpening and boundary filtering
CMSK: Privacy cover and mask
Gain: Image local gain
Multi-sensor reuse ISP, 2 sensors for maximum
Bus interface: 32bit AHB configuration, 128bit AXI R/W
Low power, auto-gating for each block
MI R/W burst group to improve memory utilization
MI 3 path output, MP stepless scaling, SP/BP scaling under 1080p
1.2.9 Audio Interface
SAI
Support audio protocol: I2S, PCM, TDM
Support up to 128 slots available with configurable size
Support slot length 8 to 32 bits configurable
Support slot valid data length 8 to 32 bits configurable
Support 2 channel TX and 2 channel RX for I2S
Audio Codec
Support one 24-bits ADC channels with 90dB SNR for stereo recording from
microphone
Support one 24-bits DAC channels with 90dB SNR for stereo playback
Support differential and single-ended microphone or line input
Sampling rate of 8KHz/12KHz/16KHz/24KHz/32KHz/44.1kHz/48KHz/96KHz
1.2.10 Connectivity
SDIO interface
Compatible with SDIO3.0 protocol
4-bit data bus widths
USB 2.0
Compatible with USB 2.0 specification
Support one USB 2.0 Host/Device
Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
Support Enhanced Host Controller Interface Specification (EHCI), Revision 1.0
Support Open Host Controller Interface Specification (OHCI), Revision 1.0a
SPI interface
Support one SPI Controllers
Support two chip-select output
Support serial-master and serial-slave mode, software-configurable
I2C Master controller
Support five I2C Master(I2C0-I2C4)
Support 7bits and 10bits address mode
Software programmable clock frequency
Data on the I2C-bus can be transferred at rates of up to 100k bits/s in the
Standard-mode, up to 400K bits/s in the Fast-mode and up to 1M bit/s in high
speed mode
UART interface
Support three UART interfaces (UART0-UART2)
Embedded two 64-byte FIFO for TX and RX operation respectively
Support 5bit, 6bit, 7bit, 8bit serial data transmit or receive
Standard asynchronous communication bits such as start, stop and parity
Support different input clock for UART operation to get up to 4Mbps baud rate
Support auto flow control mode for all UART
PWM
Support three PWM interface(PWM0-PWM2)
Support 4 channel (CH0~CH3) with interrupt-based operation
Programmable pre-scaled operation to bus clock and then further scaled
Embedded 32-bit timer/counter facility
Support capture mode
Support continuous mode or one-shot mode
Provides reference mode and output various duty-cycle waveform
Only PWM0 support one clock frequency calculation engine and one clock free
running counter
1.2.11 Others
Multiple groups of GPIO
All of GPIOs can be used to generate interrupt
Support level trigger and edge trigger interrupt
Support configurable polarity of level trigger interrupt
Support configurable rising edge, falling edge and both edge trigger interrupt
Support configurable pull direction (a weak pull-up and a weak pull-down)
Support configurable drive strength
Temperature Sensor (TS-ADC)
Support User-Defined Mode and Automatic Mode
In User-Defined Mode, start_of_conversion can be controlled completely by
software, and also can be generated by hardware.
In Automatic Mode, the temperature of alarm (high/low temperature) interrupt can
be configurable
In Automatic Mode, the temperature of system reset can be configurable
-40~125°C temperature range and +/-5°C temperature accuracy
Successive approximation ADC (SARADC)
10-bit resolution
Up to 1MS/s sampling rate
one single-ended input channels
OTP
Support 8K bits size, 7K bits for secure application
Support Program/Read/Idle mode
Package Type
RoHS QFN88 (body: 9mm x 9mm pitch 0.35mm)
1.3 Block Diagram
The following diagram shows the basic block diagram.
Chapter 2 Package Information
2.1 Order Information
2.2 Top Marking
2.2 Top Marking
原文地址：https://blog.csdn.net/mryyb123/article/details/142871442
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