Vivado HLS C/RTL 联合仿真时间
简单的led.cpp,led.h,还有一个test bench文件xxxx.cpp
source D:/Vivado_HLS_project/RGB_YCBCR_RGB/solution1/sim/verilog/xsim.dir/flash_led/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Oct 15 18:51:42 2024...
INFO: [Common 17-206] Exiting xsim at Tue Oct 15 19:10:03 2024...
INFO: [COSIM 212-316] Starting C post checking ...
shift_out is 0
shift_out is 1
shift_out is 0
shift_out is 1
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
Finished C/RTL cosimulation.
大概花了二十分钟,后面讨论时间慢的原因.
原文地址:https://blog.csdn.net/quaer/article/details/142966508
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